1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, specifically to the semiconductor device and the method thereof intended to improve breakdown voltage and inhibit leakage current by blocking the spread of a depletion layer in a peripheral area.
2. Description of the Related Art
A discrete device includes an element region where impurities are diffused on a semiconductor substrate and where a predetermined element is provided. While the discrete device is operating, a depletion layer expands from the element region (diffusion region) into the semiconductor substrate depending on applied voltage, and hereby secures breakdown voltage. However, an area is needed which prevents a surface of the substrate from inverting in a region surrounding the outer periphery of the element region.
FIG. 8 is a cross-sectional view showing a surrounding region of the conventional semiconductor devices. Here, the element region 51 is defined as a region which includes, for example, a region in which a power MOSFET 52 of a trench type is provided and a region in which a channel layer 34 and a guard ring 33 are provided in the vicinity of the region where the MOSFET 52 is provided. The guard ring 33 is a region which extends downwards deeper than the channel layer 34 and has the same conduction type with the channel layer 34. The guard ring 33 relaxes concentration of electric field which is to occur in an end of the element region 51. In addition, polysilicon 43c is connected to a gate connection electrode 48 in order to apply gate voltage to a gate electrode 43.
Furthermore, in a surrounding region 55 surrounding the outer periphery of the element region, a sealed metal 49 is provided outside the gate connection electrode 48, and an annular layer 50 in which high concentration impurities are diffused on the surface of the substrate underneath the sealed metal 49 is provided in order to prevent inversion of the substrate surface.
A description will be provided for a conventional method of manufacturing semiconductor devices with reference to FIG. 9. With regard to MOSFETs, a drain region 32 formed of an n− type epitaxial layer is formed on an n+ type silicon semiconductor substrate 31, and an n+ type annular layer 50, a p type channel layer 34 and a guard ring 33 are formed on the surface of the drain region 32. Hereafter, a trench 37 is formed which penetrates through the channel layer 34 and reaches the drain region 32 (FIG. 9A). Furthermore, an inner wall of the trench 37 is covered with a gate oxide film 41, and a gate electrode 43 is provided which is made up of polysilicon filled into the trench 37. An n+ type source region 45 is formed on the surface of the channel layer 34 adjacent to the trench 37. A p+ type body region 44 is formed on the surface of the channel layer 34 between the two source regions 45 of two MOSFET cells which are next to each other and in the outer periphery of the element region (FIG. 9B). The top of the gate electrode 43 is covered with an interlayer insulating film 46, and a source electrode 47 is provided which is in contact with the source region 45 and the body region 44. In this way, the element region 51 is formed where a plurality of MOSFETs (cells) 52 are arrayed. In addition, while the source electrode 47 is formed, the gate connection electrode 48 and the sealed metal 49 are formed (FIG. 9C).
The annular layer 50 in the surrounding region 55 is a wide diffusion region, and is formed by diffusing the high concentration impurities in a phosphorous glass diffusion process while masking in a way that only the a part of the annular layer 50 is exposed before forming the guard ring 33 and the channel region 34 (Refer to FIG. 9). A typical example of such a semiconductor device can be found in Japanese Laid-Open Patent Application No. Hei 9-331071.